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| № |
Patent number |
Title of the invention and abstract piece | Date of publication of the patent |
|---|---|---|---|
| 1 | US7570244B2 |
DISPLAY DEVICE
Signal lines for supplying signal currents to respective pixel circuits having light emitting elements are arranged. A signal line driving circuit generates, on a signal line, a signal current corresponding to the image data, by switching bit weighting currents output from bit weighting current source circuits provided for respective bits of the image data, using a switch circuit turned on/off dep... |
04.08.2009 |
| 2 | US7570447B2 |
STORAGE CONTROL DEVICE AND METHOD FOR DETECTING WRITE ERRORS TO STORAGE MEDIA
There are provided a cache region that stores write data from a host device, storage media, a data storage region for the storage media, and a comparison unit. A first comparison object is generated for N items of write data on the cache region and the N items of write data are transferred to the data storage region. Write data is read from a designated address of the data storage region and this ... |
04.08.2009 |
| 3 | US7570823B2 |
MOVING PICTURE CODING APPARATUS, MOVING PICTURE CODING METHOD, AND MOVING PICTURE IMAGING APPARATUS
When a frame (n+1) is to be inter-coded after inter-coding a frame n (S142: INTER), a moving picture coding apparatus determines a quantizer scale Q[n+1] to be used in quantization of the frame (n+1), using a first method, based on an amount of generated codes Cn of the frame n (S143). When the frame (n+1) is to be inter-coded after intra-coding the frame n (S142: INTRA), the moving picture coding... |
04.08.2009 |
| 4 | US7571268B2 |
CONSISTENT UPDATES ACROSS STORAGE SUBSYSTEMS COUPLED TO A PLURALITY OF PRIMARY AND SECONDARY UNITS AT SELECTED TIMES
Provided are a method, system, and article of manufacture, wherein a primary control unit sends a selected time to a plurality of secondary control units. Clocks are periodically synchronized at the primary control unit and the secondary control units with a time server. The primary control unit and the plurality of secondary control units consistently update secondary storage subsystems coupled t... |
04.08.2009 |
| 5 | US7571275B2 |
FLASH REAL-TIME OPERATING SYSTEM FOR SMALL EMBEDDED APPLICATIONS
A flash real time operating system for embedded applications employing flash memory is capable of storing and accessing individual bytes of data corresponding to a particular logical address in real time. The operating system writes data bytes to sequential physical blocks within the flash memory. Physical blocks written with data bytes corresponding to the same logical address are connected by a ... |
04.08.2009 |
| 6 | US7571282B2 |
COMPUTER SYSTEM HAVING A FLASH MEMORY STORAGE DEVICE
A computer system is provided, wherein a storage device having a flash memory as the main medium is given a cache memory with a high hit rate even in a small capacity and less access overheads, high-speed writing to the flash memory is attained, and the number of rewriting is reduced: wherein a processing device, a cache memory and a flash memory for data via the cache memory to be written in resp... |
04.08.2009 |
| 7 | US7571283B2 |
MECHANISM IN A MULTI-THREADED MICROPROCESSOR TO MAINTAIN BEST CASE DEMAND INSTRUCTION REDISPATCH
A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is exam... |
04.08.2009 |
| 8 | US7571302B1 |
DYNAMIC DATA DEPENDENCE TRACKING AND ITS APPLICATION TO BRANCH PREDICTION
A data dependence table in RAM relates physical register addresses to instructions such that for each instruction, the registers on whose data the instruction depends are identified. The table is updated for each instruction added to the pipeline. For a branch instruction, the table identifies the registers relevant to the branch instruction for branch prediction. |
04.08.2009 |
| 9 | US7571305B2 |
REUSING A BUFFER MEMORY AS A MICROCACHE FOR PROGRAM INSTRUCTIONS OF A DETECTED PROGRAM LOOP
A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 with... |
04.08.2009 |
| 10 | US7571345B2 |
BISECTIONAL FAULT DETECTION SYSTEM
An apparatus and program product logically divide a group of nodes and causes node pairs comprising a node from each section to communicate. Results from the communications may be analyzed to determine performance characteristics, such as bandwidth and proper connectivity. |
04.08.2009 |
| 11 | US7571351B2 |
METHOD FOR CONTROLLING A POLICY
The method includes confirmation policy processing for acquiring confirmation item information indicating a condition every confirmation item to distinguish a cause at time of fault occurrence, reading presumed cause information indicating a presumed cause corresponding to each pattern in the confirmation item information when a confirmation item value of a confirmation object satisfies a conditio... |
04.08.2009 |
| 12 | US7571360B1 |
SYSTEM AND METHOD FOR PROVIDING A CLOCK AND DATA RECOVERY CIRCUIT WITH A FAST BIT ERROR RATE SELF TEST CAPABILITY
A system and method is disclosed for providing a clock and data recovery circuit with a fast bit error rate self test capability. A bit error rate test control unit is provided that causes the clock and data recovery circuit to sample data adjacent to an edge of a bit period to create errors at a relatively high bit error rate. This is accomplished by intentionally introducing an interpolator offs... |
04.08.2009 |
| 13 | US7571371B2 |
PARALLEL PARITY CHECKING FOR CONTENT ADDRESSABLE MEMORY AND TERNARY CONTENT ADDRESSABLE MEMORY
Methods and arrangements for parallel parity checking for content addressable memory and ternary content addressable memory during compare cycles are disclosed. Further, methods and arrangements for remedying storage bit corruption are also disclosed. |
04.08.2009 |
| 14 | US7571400B2 |
CHIP DESIGN VERIFYING AND CHIP TESTING APPARATUS AND METHOD
A chip design verifying and chip testing apparatus includes a storing means for storing an application program verifying an operation of a designed chip and testing a manufactured chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the storing means and the chip, and having a data applying means for applying the I/O file and... |
04.08.2009 |
| 15 | CA2347628C |
IMPROVED SYSTEM AND METHOD FOR INTRALUMINAL IMAGING;AMELIORATION APPORTEE A UN SYSTEME ET A UN PROCEDE D'IMAGERIE INTRALUMINALE
An improved catheter system (10) having an ultrasonic imaging transducer coupled to a drive cable (34) disposed within a lumen (18) of a flexible tubular catheter body (12). An improvement including a reconfiguration of the ferrites (96, 98) in the hub assembly (24). such that the need for the gap between the ferrites is removed. A strain relief member (68) is provide to increase the strength of t... |
04.08.2009 |
| 16 | CA2414388C |
AUTOPRIMING A MICRO-CASSETTE WHILE MINIMIZING THE FORMATION OF AIR BUBBLES IN A PUMPING CHAMBER;AUTO-AMORCAGE D'UN MICROCHARGEUR AVEC MINIMISATION DE LA FORMATION DE BULLES D'AIR DANS UNE CHAMBRE DE POMPAGE
A pump used to infuse a medical liquid into a patient is autoprimed under th e control of a microprocessor that monitors and adjusts a priming sequence to minimize the accumulation of small air bubbles within a pumping chamber of t he cassette. Small air bubbles can be created by the agitation of liquid and ai r within the cassette during priming, and as a result of changing pressure conditions wi... |
04.08.2009 |
| 17 | CA2409297C |
RETRACTABLE NEEDLE AND SYRINGE COMBINATION;COMBINAISON D'UNE SERINGUE ET D'UNE AIGUILLE RETRACTABLE
A combination hypodermic syringe and needle device in which the needle is retracted inside the syringe after completion of the injection. The device requires only one hand for operation wherein increasing the pressure on the plunger initiates an automatic retraction of the needle into the syringe. In operation, a collet is expanded and a spring biased needle retractor is engaged in response to the... |
04.08.2009 |
| 18 | BRPI0800913A2 |
SISTEMA DE MONTAGEM PARA PLACAS DE PISO E/OU PAREDE
SISTEMA DE MONTAGEM PARA PLACAS DE PISO E/OU PAREDE. Este sistema inclui meios de fixação entre placas dispostos em um plano co-planar. é caracterizado pelo fato dos meios de fixação estarem determinados a partir das porções curvas em formato de ranhura localizadas na face inferior das placas e casando com as bordas laterais das placas que guiam as referidas porções curvas para convergir em tais b... |
04.08.2009 |
| 19 | US7568524B2 |
POLYPHENYLENE SULFIDE PROPPANTS
A system and method for delivering a slurry having a fracturing fluid and one or more proppants to a fracture in a subterranean formation. At least one proppant has PPS and produces less than 5 weight percent fines at a closure pressure of the fractured subterranean formation as determined by API RP 60. The one or more proppants are deposited into the fracture to prop the fracture. |
04.08.2009 |
| 20 | US7569020B2 |
METHOD FOR EXTRACTING TIMING PARAMETERS USING A CARDIO-MECHANICAL SENSOR
In a method and apparatus for measuring the ejection fraction in a mammalian heart, the opening and closing of a heart valve is sensed with an implanted sensor, and a pre-ejection period is measured as a function of the sensed opening and closing of the heart valve. The ventricular ejection time also is measured, and the ejection fraction is determined as a function of the measured pre-ejection pe... |
04.08.2009 |