A CMC-type switching regulator is disclosed that includes: a switching element switching to control outputting of input voltage; a smoothing circuit outputting the smoothed output voltage of the switching element to an output terminal; a voltage divider dividing the output voltage; an error amplifier amplifying the difference between reference voltage and the divided voltage; a slope voltage gener...

A resonance converter and a synchronous rectification driving method thereof are provided. The resonance converter includes a switch circuit having at least two first switches, a resonance circuit having a resonance frequency, a transformer, and a full-wave rectification circuit having two second switches each of which has a drain and a source and generates a channel resistance voltage when a curr...

There is provided a matrix converter apparatus including both functions of outputting a step up voltage and outputting a step down voltage. In a matrix converter apparatus for directly connecting respective phases of a three phase alternating current power source (1) and respective phases of an output side by a bidirectional switch constituted by IGBT transistors or the like connected reversely in...

Provided is an ultrasonic motor capable of realizing high torque. When two terminals are selected from a first terminal (31t), a second terminal (32t), and a third terminal (33t) of a vibrator (3), and AC voltages whose phases are shifted by 90 degrees relative to each other are respectively applied through both of those two terminals, vibration is generated in the stator vibration body (S), and e...

A direct current motor controlling method includes a mean for transforming a duty signal to computed value by a microprocessor unit. The microprocessor unit computes the computed value and then produces a target value by executing a dichotomy method, a rotation method and a transformed function, capable of reducing executing time and executing load of the microprocessor unit and saving memory spac...

Disclosed is a piezoelectric oscillator having a reduced horizontal size and being capable of being mounted in a small area. The piezoelectric oscillator includes a first package (60) and a second package (35) which are firmly connected to each other such that the second package (35) is located on the first package (60). An oscillator circuit (61) is disposed in the first package (60), and a piezo...

A data latch circuit for latching a data signal in synchronization with a clock signal includes a hold time delay unit for generating a first clock signal by delaying the clock signal for a hold time of the data signal and an inverse first clock signal as a second clock signal; a data input control unit for generating a first data transition detection signal in response to the first clock signal a...

An exemplary embodiment of an adaptive equalizer is provided, receiving symbols to generate an equalizer output. The adaptive equalizer comprises a plurality of tap cells, a coefficient updater, a plurality of multiplexers, a controller and an integrator. Each tap cell generates a filter value from a tap data value and a coefficient. The coefficient updater provides a coefficient vector comprising...

A fast wake-up crystal oscillating circuit includes: a crystal oscillator for generating oscillation signal, an amplifier set, a feedback resistor, first and second triggers and an amplifier switch logic. The amplifier set amplifies the oscillation signal. The feedback resistor supplies DC operation bias to the amplifier set. The first trigger has an input connected to the output of the amplifier ...

A clock recovery circuit capable of automatically adjusting the frequency range of a VCO (Voltage controlled Oscillator) without involving a look-up-table. The clock recovery circuit includes a main PLL (Phase locked loop) and an auxiliary PLL. The main PLL is a typical PLL for generating a main oscillation clock. The auxiliary PLL includes an auxiliary frequency detector for receiving the main os...

A method of embedding an additional layer of error correction into an error correcting code, wherein information is encoded into code words of said code over a first Galois field and wherein a number of code words are arranged in the columns of a code block comprising a user data sub-block and a parity data sub-block, provides an additional layer of error correction that can be easily implemented ...

A pattern-search based method and apparatus for context-adaptive variable length coding/decoding (CAVLC/CAVLD) is provided. The method analyzes the correlation between bit patterns and blocks. Before CAVLD, a step of bit-stream pattern search is conducted. If a pattern is matched in a look-up table, this invention skips the CAVLD procedure and reconstructs a block directly. Before CAVLC, a step of...

A method for improving the use of a secure reference principle in a header compression scheme over a channel that admits reordering of packets between a compressor and a decompressor includes transmitting a first plurality of non-context updating packets between a compressor and a decompressor over the channel and, in response to a context update, transmitting a second plurality of context-updatin...

Digital broadcasting transmission and reception devices and methods thereof are provided. The digital broadcasting transmission device includes a randomizer which randomizes a dual transport stream including a normal stream and a robust stream, a supplementary reference signal inserter which inserts a certain supplementary reference signal into a stuffing region included in the randomized dual tra...

Disclosed is an internet service system with a primary server for managing application servers coupled to it via a network. The primary server runs a program for detecting the availability and resource usage of the application servers. Each application server reports resource usage and availability to the main server program. The network has a plurality of user computers coupled to the application...

An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third current mirror having 6th-7th transistors where a current through the 2nd transistor copied from the variable current flows through t...

Methods and apparatus provide increased symbol length with more subcarriers in a fixed-bandwidth system. The subcarriers spacing may be reduced to provide increased symbol length and enable higher throughput. In one implementation, a system compatible with the IEEE P802.11n proposal can use 128 subcarriers in 20 MHz operation to provide increased throughput in lower-bandwidth channel operation.

An apparatus comprising at least one credential token interfaced with the apparatus and capable of enabling access by the apparatus to at least one network; and a peripheral link from the apparatus to at least one additional apparatus, wherein the at least one credential token enables access by the at least one additional apparatus to at least one additional network.