The present invention provides novel inhibitors of oligosaccharyl transferase, methods for producing Glc3Man9(GlcNAc)2-P-P-Dol, and methods for producing glycopeptides.

A graphics controller (IMC) which performs pointer-based and/or display list-based video refresh operations that enable screen refresh data to be assembled on a per window basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various buffers in system memory comprising video or graphics display information. The graphics controller...

A received television program is blocked out when a rating of the program is not within a scope of a preset rating. The preset rating code can be easily changed with a macro function key. A function of the macro function key is registered, and a rating code corresponding to the registered macro function key is read out. The read-out rating code is compared with a preset rating code. If the read-ou...

To visually display on a monitor screen the direction and volume of a sound source to be inserted in an image, a sound editing apparatus comprises a sound source direction setting unit for setting the sounding direction of a sound source; a sound source signal dividing unit for dividing a monaural sound source signal into left- and right-channel stereo signals according to the sounding direction o...

A processor and method of interrupt handling in a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, in response to occurrence of an interrupt during emulation of a current guest instruction, an indication of a location in memory of the current guest instruction, an indication of a location in memory o...

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from ...

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data re...

A branch prediction apparatus is provided which stores multiple branch selectors corresponding to instruction bytes within a cache line of instructions or portion thereof. The branch selectors identify a branch prediction to be selected if the corresponding instruction byte is the byte indicated by the offset of the fetch address used to fetch the cache line. Instead of comparing pointers to the b...

An information processing apparatus in which continuous data of a plurality of series in which the contents of the data of each series are related to each other with respect to time is pipeline processed by a data processing system. The apparatus comprises a plurality of sync generation circuits which correspond to the plurality of series and each of which generate sync signals to instruct timings...

In a coprocessor which processes operands and issues a result word which may include overflow, result and truncation fields and which normally sets a truncation indicator if truncation is employed, the setting of the truncation indicator is inhibited under certain conditions to facilitate later handling of the result. Determinations are made as to whether the result and truncation fields of the re...

A methodology that provides detection of cache coherency errors in addition to detection of inefficient cache use by a cache master is disclosed. A model of the cache with storage for the address and data contained in each cache line and a flag indicating the state of the cache line (e.g., MESI state, or other cache coherency protocol state) is utilized. In addition, the cache model object also ho...

An intermediate result signal arising from a manipulation of data signals is checked and reduced without using conditional branches, thereby improving instruction processing. Data signals are represented as signed 8-bit binary values in a two's compliment format. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper check...

The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identi...

A central processing unit (CPU) of a computer includes a novel prefetch cache configured in parallel with a conventional data cache. If a data cache miss occurs, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, a prefetch address is derived, and data corresponding to the prefetch address is pr...

An address translation memory stores a plurality of virtual address tags. The virtual address tags typically designate a portion of the virtual address space corresponding to a page of data stored in an intermediate storage device. A portion of an input virtual address is used to address the translation memory, and the resulting output virtual address tag is compared to a relevant portion of the i...

The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers. Therefore, there have to exist several physical rename registers per logical register. The oldest ...

A method for guaranteeing minimum variable scheduling distance between instructions in a processor includes receiving a plurality of instructions and determining the post-ready latency of each instruction. Each instruction is then scheduled for execution so that the instruction follows an earlier instruction by an amount of time at least equal to the post-ready latency of the instruction.

An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

A enable circuit (700), employing a "circular carry lookahead" technique to increase its speed performance, is provided for applying two pointers to a circular buffer-an enabling pointer (tail <3:0> (218)) and a disabling pointer (head <3:0> (216))-and for generating a multiple-bit enable, ENA (722) in accordance with the pointer values. The pointers designate enable bit boundaries for isolating e...

A circuit and a scheme for register renaming responsive to a thread ID register, comprises: a plurality of physical registers; a plurality of architectual registers; a rename logic circuit where every write to an architectual register of the plurality of architectural registers is assigned a new physical register of the plurality of physical registers; a register map circuit containing a correspon...