Результати пошуку

з
 
  


п/п
Номер
патенту
Назва винаходу та фрагмент реферату Дата публікації патента
1 TWI318914B
<назва відсутня>

A pressure regulating mechanism for use in a pneumatic tool includes a first relief valve and a second relief valve. The pneumatic tool includes a housing having an air intake passage, an exhaust passage and a connecting passage in air communication between the air intake passage and the exhaust passage, an air cylinder unit mounted in the housing. The air cylinder unit has an air chamber, an air ...

01.01.2010
2 TWI318915B
<назва відсутня>

The present invention provides an improved structure for a power tool, which comprises a driving device, a chuck device, and a storage device. The driving device is installed in the power tool to produce a power. The chuck device is installed at a front end of power tool to clamp and hold a tool bit. The storage device comprises a hollow power shaft which is connected with one end of the driving d...

01.01.2010
3 TWI318916B
<назва відсутня>

A digital torque wrench(1)includes a wrench head having a head part and a strain segment extended from the head part. At least a strain gauge is installed on the strain segment. A main body is combined with the wrench head. An electromagnetic device is installed in the main body and corresponds to the wrench head. The presence or not of an attraction/repulsion electromagnetic force is used to rele...

01.01.2010
4 TWI319188B
METHOD OF OPERATING MULTI-LEVEL CELL

A method of operating a multi-level cell is described, wherein the cell includes a substrate of a first conductivity type, a control gate, a charge-storing layer and two S/D regions of a second conductivity type. The method includes an erasing step that injects charges of a first type into the charge-storing layer and a programming step that includes applying a first voltage to the substrate, a se...

01.01.2010
5 TWI319189B
<назва відсутня>
01.01.2010
6 TWI319190B
METHOD AND APPARATUS FOR PROGRAMMING NONVOLATILE MEMORY

Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.

01.01.2010
7 TWI319191B
SOLID STATE DISK CONTROLLER APPARATUS AND OPERATING METHOD THEREOF

A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and writ...

01.01.2010
8 TWI319192B
METHOD AND SYSTEM FOR PREVENTING NOISE DISTURBANCE IN HIGH SPEED, LOW POWER MEMORY
01.01.2010
9 TWI319193B
METHOD AND APPARATUS TO CONTROL SENSING TIME FOR NONVOLATILE MEMORY

One or more clock signals are used to control sense amplifier measurements. For example, multiple threshold voltage measurement types characterize the multiple clock signals, and selecting the appropriate clock signal selects the appropriate measurement type. In another example, multiple clock signals control multiple measurements of a particular location of nonvolatile memory, so that one of mult...

01.01.2010
10 TWI319194B
MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE

A multi-port memory device includes: a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a plurality of banks arranged at upper and lower regions of the multi-port memory device in a row direction on the basis of the plurality of ports; and first and second global I/O data buses arranged int...

01.01.2010
11 TWI319195B
METHOD AND APPARATUS FOR READING DATA FROM NONVOLATILE MEMORY

Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory cells bracket second current path terminals of the target memory cells electrically along the wo...

01.01.2010
12 TWI319196B
ELECTROSTATIC DISCHARGE PROTECTION CIRCUI

An electrostatic discharge (ESD) protection circuit is provided. The circuit includes at least one fuse cell and a metal oxide semiconductor field effect transistor (MOSFET). Each of the fuse cells includes a fuse and outputs a bit data according to whether the fuse is melted or not. The MOSFET has a first terminal coupled to each of the fuse cells and a second terminal coupled to a voltage source...

01.01.2010
13 TWI319197B
MEMORY CHIP ARCHITECTURE WITH HIGH SPEED OPERATION

A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory devic...

01.01.2010
14 TWI319198B
ADJUSTABLE TERMINATION RESISTOR DEVICE UED IN IC CHIP

An adjustable termination resistor includes a reference resistor, a current mirror circuit, a calibration transistor-resistor array, a digital code generator, a comparator, a decision and latch circuit and a termination resistor. The mirror current generated from the current mirror circuit flows through the calibration transistor-resistor array to result in a comparing voltage across the calibrati...

01.01.2010
15 TWI319199B
ELECTRON FLOOD APPARATUS AND ION IMPLANTATION SYSTEM

An electron flood apparatus 1 of the present invention comprises a chamber 22 having a first part 22 a made of conductive material and a second part 22 b made of insulating material, and extending along a predefined closed curve Ax. A coil 18 is provided outside the first part 22 a to generate a magnetic field in a direction intersecting with the surface formed by the predefined closed curve Ax. T...

01.01.2010
16 TWI319200B
FLAT LIGHT MODULE AND MANUFACTURING METHOD THEREOF

A flat light module and the manufacturing method thereof are disclosed. A first substrate and a second substrate with a plurality of electrodes are assembled. The discharge gas is filled between both substrates. A first dielectric layer with a first pattern and a second dielectric layer with a second pattern are covered on the electrodes in order, wherein the first pattern is used as a stopper and...

01.01.2010
17 TWI319201B
APPLICATIONS OF NANO-ENABLED LARGE AREA MACROELECTRONIC SUBSTRATES INCORPORATING NANOWIRES AND NANOWIRE COMPOSITES

Macroelectronic substrate materials incorporating nanowires are describes. These are used to provide underlying electronic elements (e.g., transistors and the like) for a variety of different applications. Methods for making the macroelectronic substrate materials are disclosed. One application is for transmission an reception of RF signals in small, lightweight sensors. Such sensors can be config...

01.01.2010
18 TWI319202B
<назва відсутня>

An amorphous Si (silicon)/Au (gold) eutectic wafer bonding structure is fabricated. An amorphous Si obtained through coating or growth contacts with Au for bonding. The bonding layer is a Si/Au eutectic layer. Si is prevented from being precipitated. The bonding structure has a fast reaction ratio and a uniformed reaction. Thus, an electrical device has an improved electricity and reliability.

01.01.2010
19 TWI319203B
CLEANING COMPOSITION SOLUTION AND METHOD OF CLEANING WAFERS USING THE SAME
01.01.2010
20 TWI319204B
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING TUNGSTEN AS SACRIFICIAL HARD MASK

The present invention relates to a method for fabricating a semiconductor device using tungsten as a sacrificial hard mask material. The method includes the steps of: forming a layer on an etch target layer; forming a photoresist pattern on the layer; etching the layer by using the photoresist pattern as an etch mask along with use of a plasma containing CHF3 gas to form a sacrificial h...

01.01.2010