PURPOSE: To improve the production efficiency of a spiral finned tube by automatically cutting a fin material at a position avoiding a pressure roll. CONSTITUTION: In a device manufacturing the spiral firmed tube wherein a fin material 2 is welded on a tube 1 while a linear band shaped fin material 2 is spirally coiled on the outer peripheral surface 4 of the tube 1, a cutter 12, which cuts the li...

PURPOSE: To provide the power unit of an electric vehicle to reduce a cost and have sufficient rigidity. CONSTITUTION: The power unit of an electric vehicle wherein an electric motor 46 and a differential gear 47 and loaded on a subframe 37 and a drive wheel 48 mounted on the output shaft of the electric motor 36 and a driven wheel 49 mounted on the input shaft of a differential gear 47 are interc...

A breast prosthesis comprises a shell-like body of a two-component cross-linked soft elastic silicone rubber composition, which is welded in synthetic resin films, which cover over its inner and outer surfaces. In order to secure the breast prosthesis directly to the skin of the user, the prosthesis is so designed that on its rear side, in a marginal zone, it is furnished with a permanently adhesi...

A process for forming a permanently elastic adhesive connection, easily detachable in the case of disassembly, especially adhesive connections made of temperature-stable silicone compounds, between a plate made of glass, glass ceramic or a similar material, from a holding frame on which the plate rests. In particular, the process can be used to provide such an adhesive connection between a cooking...

A pattern of tear perforations is provided in the substrate that forms a microwave reheating support. The pattern of tear perforations enables the substrate to be separated into portions so that the substrate can be adjusted in size and/or shape to correspond to the size and/or shape of the food product being heated. For example, a round substrate can include a circular pattern of tear perforation...

Peptides capable of binding calmodulin are disclosed. The peptides surprisingly do not exhibit strict alpha -helical conformations.

A lead frame for a semiconductor IC device has a pair of common elongated leads and first and second groups of slender leads arranged on opposite sides of the common elongated leads and generally extending transverse to the common elongated leads. The common elongated leads have as their integral parts slender leads extending therefrom generally transverse thereto and substantially linear extensio...

Disclosed herein is a semiconductor device package including a ground frame formed of a metal plate. The ground frame has a rectangular central portion, four legs integrally extending outward from the four corners of the central portion, and four grounding lead terminals formed integrally with the outer ends of the four legs. The width of each grounding lead terminal including a grounding portion ...

An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition for performance of the second operation. Instead of performing zero detection on the result, zero prediction is performed on the initial or intermediate operands, (e.g., partial products that are summed to...

Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has a master latch to receive and store an external address. A first slave latch is also included to receive and store the external address from the master latch if the external address belongs to the first bank and to provide the external address ...

An interface circuit for keyboards and other serial peripheral devices that adds loopback capability through multiplexers in the clock and data lines, and also provides a receiver clock delayed from the transmitter clock to avoid race conditions between the data and clock lines. The circuit also provides a means of forcing a zero bit onto the data line after a byte is sent, to indicate to the tran...

A parity bit memory simulator including a parity bit memory formed of a single bit memory of fixed address length, which replaces the single bit parity RAM of variable address length of conventional memory modules, is connected with its address signal line to the data bus of the memory module so that the parity bit memory provides and stores parity bits for the computer system without changing the...

An intelligent status monitoring, reporting and control module is coupled to a SCSI bus that interconnects a cluster of SCSI-compatible data storage modules (e.g., magnetic disk drives). The status monitoring, reporting and control module is otherwise coupled to the cluster of SCSI-compatible data storage modules and to power maintenance and/or other maintenance subsystems of the cluster for monit...

A data processing device includes a data bus and a program bus, a data memory connected to the data bus and having data memory locations, and an electronic computation unit connected to the data bus and an accumulator connected to the electronic computation unit and to the data bus. A logic circuit is connected to the program bus for receiving instructions and connected to the data bus for executi...

Apparatus for determining the length of an instruction being processed by a computer system when instructions vary in length and appear sequentially in an instruction stream without differentiation between instructions including apparatus for providing an end bit for each predesignated length of an instruction to indicate that the instruction ends at that point in its length, apparatus for setting...

The STREAMER FOR RISC DIGITAL SIGNAL PROCESSOR shown herein allows a CPU 46 to interface with a memory 60 via data registers 50. Pre-fetch and post-store of the correct address is determined by an address generator 58 according to a rule determined by a context register 52. An index indicative of this address is stored in an index register 54. The data, context, and index registers together form a...

A solid state memory disk with increased reserve memory is described. The solid state memory disk includes an array of solid state memory devices for storing user data and reserve memory, which includes both free memory and dirty memory. The solid state memory disk also includes a controller, a clean-up state machine, and a data compressor. The data compressor increases reserve memory by compressi...

An integrated circuit chip includes a processor (4) and a memory (10) coupled by data and address buses (PAB, PDB). The memory is switchable between a first, standard, mode of operation in which a memory controller (14) is operative and a second, cache, mode of operation in which a cache controller (12) is operative by a switch (16, 22, 40). A memory area includes a valid bits array (VBA), a bit o...

A cache memory system features a combination instruction cache and prefetch buffer, which obviates any requirement for a bus interconnecting the cache and buffer and which also effectively allows the instruction buffer to write data into the cache with improved utilization of prefetched instructions and with decreased use of power and silicon space.

A method and a structure provide a flexible cache module for use in cache memory performance modelling. The flexible cache module can be configured by jumper connections or switches into a cache memory having a line size and a cache size selectable from a number of combinations of line size and cache size. In addition, the flexible cache module can also be configured as either a split cache memory...