An electronic ballast circuit and related method for enabling full range dimming of a gas discharge load such as a compact fluorescent lamp.

An embodiment of a method for driving a phase change memory, comprising counting an access number of a phase change memory, wherein the access number is the number of times that the phase change memory has been accessed; refreshing the phase change memory when the number of times is large than a predetermined number.

A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows do...

A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is the source of the selected memory cell while applying a drain programming voltage to a second bit line that forms a d...

A self refresh circuit includes a refresh control unit and an internal refresh circuit. The refresh control unit generates a refresh control signal based on a refresh period pulse when a MRS (Mode Set Register) command is deactivated, interrupts an output of the refresh control signal based on a self-refresh-entrance inhibiting signal when the MRS command is deactivated, and generates a refresh co...

An apparatus included in a semiconductor memory device for precharging a bit line and a bit line bar and sensing and amplifying a data delivered to one of the bit line and the bit line bar. The apparatus includes a precharge block for precharging the bit line and the bit line bar as a ground, and a sense amplifying block for sensing and amplifying the data by using a core voltage for operating the...

This invention relates to a memory storage device, including: a printed circuit board for carrying the following components; a memory module placed on the printed circuit board, and having a first storage area and a second storage area; a mapping table; and a controller placed on the printed circuit board and coupled to the memory module and the mapping table, and the controller being able to reco...

A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strob...

An apparatus for generating an internal address of a semiconductor memory device is provided to reduce the layout size and current consumption of the semiconductor memory device by controlling the output timing of an address according to a signal, which is activated correspondingly to a preset latency. An apparatus for generating an internal address of a semiconductor memory device includes a pipe...

A first intensity Az expressed as Az=azxEalpha, a first reference intensity A0 expressed as A0=a0xEalpha, a second intensity Bz expressed as Bz=bzxE, and a second reference intensity B0=b0xE, are evaluated. The first intensity and the first reference intensity are of radioactive nuclides generated by a neutron capture reaction of a heavy nuclide or a fission product nuclide. The second intensity a...

In a solid electrolytic capacitor including a device portion having a cathode conductor layer and an anode conductor layer arranged on a sheet-like or a foil-like base member, a first insulating resin layer is formed on the cathode conductor layer and the anode conductor layer. A positive electrode mounting terminal layer is formed on the first insulating resin layer. An anode conductor portion pe...

A solid electrolytic capacitor having multiple capacitor elements and a lead frame is provided. Each capacitor element includes an anode part, a cathode part, an insulating part and at least one first slit. The cathode part is disposed opposite to the anode part. The insulating part is disposed between the anode part and the cathode part. The first slit is disposed at the anode part. The lead fram...

A cold electron infrared ray lamp is disclosed comprises a sealed glass tube, a planar anode, a planar cathode, and a focus lens. The planar anode and the planar cathode are disposed on grooves of a supporting base and then sealed thereafter. The cathode is formed of a nickel plate grown with a carbon film thereon. The anode is formed of a fluorescence layer, an indium tin oxide layer, and a glass...

A method for changing an amorphous silicon film to a polycrystalline silicon film includes the steps of irradiating an elongate pulse laser beam onto the silicon film while scanning in the direction normal to the major axis of the elongate pulse laser beam, to form a plurality of irradiated areas, irradiating flat-surface light onto the irradiated areas in the direction parallel to the major axis,...

Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may comprise a substrate having a first surface and a second, opposing surface, and a through-wafer interconnect extending into the first surface of the substrate. The through-wafer interconnect may include an electrically conductive material extend...