A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.

A microelectromechanical system (MEMS) device may include a substrate and at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least...

PROBLEM TO BE SOLVED: To provide a method for manufacturing a flash memory device with which endurance property can be improved without deteriorating program disturbance property. Ž

SOLUTION: The method for manufacturing a flash memory device includes the steps of forming a stack gate constituted by stacking a tunnel dielectric film, polysilicon film pattern for floating gate, inter-layer die...

A semiconductor device having contact surfaces of different heights electrically connected to conductors defined on one or more patterned metal planes and a method for fabricating the semiconductor device. In one embodiment, the semiconductor device comprises a substrate having a process surface; a first contact and a second contact arranged on the substrate, a second contact surface of the second...

A molding apparatus at least includes a mold and a machine. The mold has at least a molding hole and a transfer pot. Every molding hole corresponds to every transfer pot. A molding compound is contained in the transfer pot and filled into the whole molding hole. The machine has a sensor which is sensing the molding hole if is bad, and then connects to the mold and not molds the bad molding hole.

Disclosed is an interposer comprising a silicon substrate (20). A plurality of conductive holes (27) penetrating the silicon substrate (20) are formed by dry etching, and at least one end of each conductive hole (27) is provided with a probe (12) via a pad (45). Since conductive holes are formed in a substrate that can be processed by dry etching, a plurality of microscopic conductive holes can be...

A heat sink for conducting a coolant is provided. The heat sink includes a casing and a porous material layer. The porous material layer is disposed inside the casing, and the coolant is conducted into the porous material layer. Moreover, a package structure that dissipates heat by use of a coolant is provided. The package structure includes a carrier, a chip, and the aforementioned heat sink. The...

A LED package includes a LED chip and a flexible carrier, wherein the LED chip has a plurality of electrodes. The flexible carrier has a flexible substrate and a circuit layer, wherein the flexible substrate has a support surface and a back surface opposite the support surface, and the circuit layer is disposed on the support surface. In addition, the LED package further includes a plurality of bu...

Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first materi...

A pad structure 100 includes an electrode pad (a first electrically conducting film 104 and a second electrically conducting film 110) and an insulating film provided over a peripheral region of the electrode pad so as to surround the electrode pad, and the insulating film has a structure including a protective film (a cover oxide film 106) and a transparent resin film (a transparent resin 108) pr...

The present invention provides a semiconductor device and a manufacturing method thereof which can make a ground/power source potential stable without reducing the number of pins for signals. The semiconductor device includes a plurality of leads, a tab having a size smaller than a size of a semiconductor chip, suspending leads connected to the tab and having suspending lead exposing portions, fou...

A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit bloc...

The present invention provides a package structure with lead-frame on stacked chips, comprising: a lead-frame, composed of a plurality of outer leads arranged in rows facing each other and a plurality of inner leads arranged in rows facing each other formed by a plurality of wires, wherein the plurality of inner leads are divided into first inner leads and second inner leads, and the length of the...

The invention provides a multi-package module (MPM). The multi-package module includes a first package, a plurality of second packages, a plurality of electrical connecters positioned in the joints of the packages, a plurality of solder balls positioned on the outer side of the first package, and a plurality of heat-dissipating devices positioned on the first and the second packages. The first pac...

A method ( 10 ) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors ( 150 ) and partially-depleted silicon-on-insulator (FD-SOI) transistors ( 152 ) on a semiconductor substrate ( 104 ) as part of an integrated circuit fabrication process is disclosed.

A high-quality, substantially relaxed SiGe-on-insulator substrate material which may be used as a template for strained Si is described. The substantially relaxed SiGe-on-insulator substrate includes a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially relaxed SiGe layer present atop the insulating region. T...

A back-illuminated type solid-state image pickup device (1041) includes read circuits (Tr1, Tr2) formed on one surface of a semiconductor substrate (1042) to read a signal from a photo-electric conversion element (PD) formed on the semiconductor substrate (1042), in which electric charges (e) generated in a photo-electric conversion region (1052c1) formed under at least one portion of the read cir...