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| № п/п |
Номер патенту |
Назва винаходу та фрагмент реферату | Дата публікації патента |
|---|---|---|---|
| 1 | US7404500B2 |
PILL DISPENSING DEVICE
A pill dispensing cap for a bottle has an inner sleeve with a divider panel and a first base panel rotatable within an outer sleeve having a second base panel. First and second window openings are defined in the first and second base panels. A plate moveable across and within the two sleeves defines a third window opening and a fourth window opening is defined in the divider panel. The plate can b... |
29.07.2008 |
| 2 | US7404707B2 |
SAMPLE MOUNTING PRESS
A hydraulic sample mounting press utilizes a face seal against the top face of a molding cylinder. The face seal employs a hydraulic cylinder to press a disk-shaped surface of a cap piece against the top annular face of the mold cylinder for a metallographic mounting press. The face seal cylinder is mounted to a hydraulic fluid column that allows the face seal to rotate away from the mold cylinder... |
29.07.2008 |
| 3 | US7404948B2 |
PEPTIDIC CONJUGATES FOR ALOPECIA PREVENTION AND TREATMENT
The invention relates to novel peptidic conjugates containing a Gly-His-Lys sequence and used for dermatology or cosmetology for stimulating hair growth or stopping hair fall. |
29.07.2008 |
| 4 | US7405104B2 |
LEAD FRAME AND METHOD OF PRODUCING THE SAME, AND RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME
A resin-encapsulated semiconductor device includes a semiconductor chip, a plurality of inner leads that are connected to a group of electrodes of the semiconductor chip, respectively, and an encapsulating resin that encapsulates a connection part located between the semiconductor chip and the inner leads. Each of the inner leads includes a protruded portion provided on a surface thereof on an out... |
29.07.2008 |
| 5 | US7405980B1 |
SHARED TERMINAL MEMORY INTERFACE
A memory architecture for a disk drive system in which Synchronous Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two memory components are provided to improve performance of the system, as well as reduce pin count and cost. An integrated circuit memory ... |
29.07.2008 |
| 6 | US7406154B2 |
HIGH SPEED MODULATION OF SWITCHED-FOCUS X-RAY TUBE
A dose-modulated irradiating system includes an x-ray tube ( 20 ) with at least a filament ( 80 ) for generating electrons, a cathode ( 84 ) and an anode ( 92 ) for accelerating and collimating the generated electrons into an electron beam ( 94 ), and an electrostatic grid with grid electrodes ( 110, 112 ) for steering the electron beam ( 94 ) on the anode ( 92 ). The anode ( 92 ) generates an x-r... |
29.07.2008 |
| 7 | US7406239B2 |
OPTICAL ELEMENTS CONTAINING A POLYMER FIBER WEAVE
A polarizer is formed with an arrangement of polymer fibers substantially parallel within a polymer matrix. The polymer fibers are formed of at least first and second polymer materials. At least one of the polymer matrix and the first and second polymer materials is birefringent, and provides a birefringent interface with the adjacent material. Light is reflected and/or scattered at the birefringe... |
29.07.2008 |
| 8 | US7406406B2 |
INSTRUCTIONS TO LOAD AND STORE CONTAINING WORDS IN A COMPUTER SYSTEM EMULATOR WITH HOST WORD SIZE LARGER THAN THAT OF EMULATED MACHINE
Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a "containing" word stored in the memory of the host machine. A "LOAD64" instruction loads the emulator memory location representing an emulated "Q" (supplementary accumulator) register with the "no... |
29.07.2008 |
| 9 | US7406560B2 |
USING MULTIPLE NON-VOLATILE MEMORY DEVICES TO STORE DATA IN A COMPUTER SYSTEM
Provided are a method, system, and machine readable medium for using multiple non-volatile memory devices to store data in a computer system. Access to a first and second memory devices are managed. The first memory device has faster read access and slower write access relative to the second memory device and the second memory device has slower read access and faster write access relative to the f... |
29.07.2008 |
| 10 | US7406565B2 |
MULTI-PROCESSOR SYSTEMS AND METHODS FOR BACKUP FOR NON-COHERENT SPECULATIVE FILLS
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruct... |
29.07.2008 |
| 11 | US7406569B2 |
INSTRUCTION CACHE WAY PREDICTION FOR JUMP TARGETS
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instruction... |
29.07.2008 |
| 12 | US7406585B2 |
DATA PROCESSING SYSTEM HAVING AN EXTERNAL INSTRUCTION SET AND AN INTERNAL INSTRUCTION SET
There is provided a system having an execution core operable to execute internal instructions. A translation buffer is operable to store a plurality of internal instruction blocks of one or more internal instructions where the internal instruction blocks are a dynamic translation of respective external instruction blocks of one or more external instructions. A remapper is responsive to an executio... |
29.07.2008 |
| 13 | US7406589B2 |
PROCESSOR HAVING EFFICIENT FUNCTION ESTIMATE INSTRUCTIONS
High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolatio... |
29.07.2008 |
| 14 | US7406628B2 |
SIMULATED ERROR INJECTION SYSTEM IN TARGET DEVICE FOR TESTING HOST SYSTEM
A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a command. Based on the interrupt signal and a stored error mode page, a false error condition is initiated by further programming the sequencer to operate abnormally. After recovery from the error condition, th... |
29.07.2008 |
| 15 | US7406649B2 |
SEMICONDUCTOR MEMORY DEVICE AND SIGNAL PROCESSING SYSTEM
The disclosed semiconductor memory device exhibits improved error correction capability shorter read/write times, and removes or reduces the need for redundant memory The semiconductor device has a data input portion for receiving one page of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words, and ... |
29.07.2008 |
| 16 | SG143932A1 |
PACKAGED MICROELECTRONIC DEVICES AND METHODS OF PACKAGING MICROELECTRONIC DEVICES
PACKAGED MICROELECTRONIC DEVICES AND METHODS OF PACKAGING MICROELECTRONIC DEVICES Packaged microelectronic devices and methods of packaging microelectronic devices are disclosed herein, In one embodiment, the device includes en Image sensor die having a first side with a bend-pad, an active area on the first side, and a second side opposite the first side. The device further includes a window at t... |
29.07.2008 |
| 17 | SG143984A1 |
BENEFICIATED WATER REDUCING COMPOSITIONS
BENEFICIATED WATER REDUCING COMPOSITIONS Exemplary compositions comprise at least one aldopentonic acid, such as xylonic acid; and further comprise a lignin, a lignosulfonic acid or its salt, an additional sugar acid such as a aldohexonic acid or salt, a conventional admixture (such as a polyacrylate superplasticizer, a corrosion inhibitor, a set retard, a set accelerator, etc.), or a mixture ther... |
29.07.2008 |
| 18 | SG144054A1 |
PREFETCHING FROM A DYNAMIC RANDOM ACESS MEMORY TO A STATIC RANDOM ACCESS MEMORY
PREFETCHING FROM A DYNAMIC RANDOM ACESS MEMORY TO A STATIC RANDOM ACCESS MEMORY Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer tw... |
29.07.2008 |
| 19 | CA2285673C |
CYCLIC ANALOGS OF HISTATINS;ANALOGUES CYCLIQUES DE COMPOSES D'HISTATINE
Cyclic analogues of histatin H-5, having from about 7 - 20 amino acid units exhibiting substantial homology to histatin H-5, and having a cyclic portion of from 5 -16 of the amino acid units, have been found to exhibit enhanced bio- activity against a variety of different microorganisms. The cyclic structure is imparted by replacement of naturally occurring amino acids in histatin-5 sequences by, ... |
29.07.2008 |
| 20 | CA2314863C |
RADIAL HEAD IMPLANT SYSTEM INCLUDING MODULAR IMPLANTS, SIZERS AND INSTRUMENTATION;SYSTEME D'IMPLANT DE TETE RADIALE COMPRENANT DES IMPLANTS MODULAIRES, DES ELEMENTS DE COLLAGE ET DES INSTRUMENTS
A system including modular radial head implants, sizers for trial reduction of the joint, and instrumentation for preparing the radial head, implanting the sizers, assembling the implants. |
29.07.2008 |